1. Field of the Invention
The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to the protection of memory consistency in a multiprocessor computing system.
2. Description of the Related Art
Modern needs for high-powered computing systems have resulted in the development of multiprocessor computer architectures having two, four, eight or more separate processors. Such multiprocessor systems are able to execute multiple portions of program code simultaneously, typically in the form of multiple processes and/or multiple process threads. Further, most modern multiprocessor computing systems support shared memory that is accessible by two or more code portions (e.g. processes or threads) running on separate processors.
It is important that any changes to the data stored in the shared memory are made visible to each of the multiple code portions in an orderly and synchronised manner. Hence, each different type of multiprocessor system has its own corresponding memory consistency model that specifies the semantics of memory operations (particularly relating to load, store and atomic operations) that thereby defines the way in which changes to shared memory are made visible in each of the multiple processors. The program code and the hardware in the multiprocessor system should both adhere to the memory consistency model in order to achieve correct operation. Conversely, a memory consistency failure may lead to a fatal crash of the system.
A more detailed introduction to memory consistency models in multiprocessor computing systems is provided in “Shared Memory Consistency Models: A Tutorial” by Sarita V. Advey and Kourosh Gharachorlooz, published as Rice University ECE Technical Report 9512 and Western Research Laboratory Research Report 95/7 dated September 1995, the disclosure which is incorporated herein by reference.
In the simplest example, the memory consistency model specifies sequential consistency whereby the memory operations appear to take place strictly in program order as specified in the program code. However, the processors and memory subsystems in a multiprocessor architecture are often designed to reorder memory operations to achieve improved hardware performance. That is, many modern shared-memory multiprocessor systems such as Digital ALPHA, SPARC v8 & v9 and IBM POWER and others provide various forms of relaxed ordering and offer subtly different forms of non-sequential memory consistency. Here, further general background information in the field of memory consistency is provided in an article entitled “POWER4 and shared memory synchronisation” by B. Hay and G. Hook at http://www-128.ibm.com/developerworks/eserver/articles/power4_mem.html of 24 Apr. 2002, the disclosure of which is incorporated herein by reference.
This memory consistency issue becomes particularly acute in the field of program code conversion, and especially so in relation to dynamic binary translation. Here, program code written or compiled specifically to run on a first type of multiprocessor computer architecture (here called the subject architecture) is translated and executed instead on a second type of multiprocessor computer architecture (the target). For example, binary code for the SPARC v9 subject architecture is dynamically translated and executed as binary code on a POWER target architecture. However, the memory consistency model of the target architecture often deviates from the model of the subject architecture. In particular, memory consistency errors arise when converting program code from a subject architecture having a strongly-ordered memory consistency model (such as SPARC and x86 architectures) to a target architecture having a memory consistency model with relatively weak ordering (such as in PowerPC and Itanium architectures).
An aim of at least some exemplary embodiments of the present invention is to provide a multiprocessor computer system in which memory consistency errors are reduced. Another aim of at least some exemplary embodiments of the present invention is to provide a multiprocessor computer system in which memory consistency errors are reduced when executing code produced by automatic program code conversion such as dynamic binary translation.